AMD To Show Off Bulldozer 32nm Processor at ISSCC 2011
We just got word from AMD that later this week at the International Solid State Circuits Conference (ISSCC) in San Francisco the company will be announcing some more information on Bulldozer! From what we can tell the company will be talking more about the Bulldozer Integer Unit (EX) and Floating-Point Unit (FPU) in more detail than ever before.
At ISSCC well be covering new details throughout the week. For example: The Bulldozer core circuit design is described in detail in ISSCC paper (Session 4.5) titled Design Solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU (http://isscc.org/program/index.html). This paper describes design techniques used to wring maximum performance from the GLOBALFOUNDRIES 32nm SOI manufacturing process. Changes in clocking, latching, power management and on-chip memories are part of the comprehensive circuit updates incorporated into Bulldozer. These are detailed in the paper, along with significant power reduction improvements, including clock gating, a new low-power flop design, and L1 cache power improvements.
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